...the prerequisites:
Overview HC12 Derivatives
| HC812A4 | HC912B32 | HC912BC32 | HC912D60/ HC912D60A |
HC912DG128/ HC912DG128A |
9S12DP256 | |
|---|---|---|---|---|---|---|
| CPU Core | CPU12 | CPU12 | CPU12 | CPU12 | CPU12 | HCS12 |
| Operating Voltage | 4.5-5.5V | 4.5-5.5V | 4.5-5.5V | 4.5-5.5V | 4.5-5.5V | 4.75-5.25V |
| Flash | - | 32K | 32K | 60K (f) | 128K (f) | 256K |
| EEPROM | 4K | 768 | 768 | 1K | 2K | 4K |
| RAM | 1K | 1K | 1K | 2K | 8K | 12K |
| Bus Interface | Non-MUX (a) | MUX | MUX | MUX | MUX | MUX |
| Bus Clock ECLK max. | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 25 MHz |
| PLL | x | - | - | x | x | x |
| Timer Module | TIM | TIM | TIM | ECT | ECT | ECT |
| PWM (Ch. x Bit) | - | 4 x 8 (b) | 4 x 8 (b) | 4 x 8 (b) | 4 x 8 (b) | 8 x 8 (c) |
| SCI | 2 | 1 | 1 | 2 (e) | 2 | 2 |
| SPI | 1 | 1 | 1 | 1 | 1 | 3 |
| IIC | - | - | - | - | 1 | 1 |
| CAN | - | - | 1 | 1 | 2 | 5 |
| BDLC | - | 1 | - | - | - | 1 |
| ADC (Ch x Bit) | 8 x 8 | 8 x 10 | 8 x 10 | 16 x 10 / 8 x 10 |
16 x 10 | 16 x 10 |
| BDM | x (d) | x | x | x | x | x |
| I/O Lines (max. ohne PORTE) |
85 | 55 | 55 | 80 / 52 | 81 | 83 |
| Key-Wakeup Lines | 24 | - | - | 15 / 2 | 16 | 20 |
| Package | TQFP112 | QFP80 | QFP80 | TQFP112 / QFP80 |
TQFP112 | TQFP112 |
(a) supports Memory Pageing (max. 5 MB), 7 Chip Selects
(b) or 2 x 16
(c) or 4 x 16
(d) no Hardware Breakpoints
(e) optional: 1x SCI + 1x MI-BUS
(f) D60A/DG128A with improved Flash Memory Module
TIM = Standard Timer Module
ECT = Enhanced Capture Timer
MUX = Multiplexed External Bus Interface
Non-MUX = Non-Multiplexed Ext. Bus Interface